Relates to the RISC-V ISA. All Bare Metal RISC-V tutorials will be grouped under this tag.

RISC-V Bare Metal Programming - Chapter 5: It's a Trap!

Submitted by MarcAdmin on Tue, 12/10/2019 - 21:36
Up to this point, the RISC-V tutorial has focused on single applications running on a single hardware thread. The application's environment was composed of the processor's state and memory map. The processor state was controlled via assembly instructions, and the memory map was defined at build time via a linker script. However, modern systems are almost always multiprogrammed and will execute many applications concurrently (by interleaving their instructions in a single stream). Moreover, multiple hardware threads are common, allowing application instructions to execute simultaneously. This workflow requires a lot more care to ensure correctness and proper separation of memory. This idea was touched upon briefly in chapter 4 while discussing the A extension which provides atomic memory operations that were used to define synchronization primitives. In addition to memory synchronization, the application must control the execution environment of all of the active hardware threads, this chapter will explore the mechanisms available for this purpose.

RISC-V Bare Metal Programming - Chapter 4: Another Brick in the Wall

Submitted by MarcAdmin on Sat, 11/30/2019 - 01:41
Chapter 3 of this RISC-V bare metal tutorial studied the linking process and how a developer can control where code and data are placed in memory. Constants, initialized variables and uninitialized variables were defined and explicitly positioned in RAM as prescribed by a linker script. The running example program was updated to read operands from RAM to perform its task, and subsequently store the result in a different location in RAM. However, up to this point only the base RV64I instruction set has been used. This chapter will explore some of the standard extensions available in the RISC-V ISA.


RISC-V Bare Metal Programming Chapter 3: A Link to the Past

Submitted by MarcAdmin on Tue, 11/12/2019 - 12:27

Previous chapters of the RISC-V bare metal programming tutorial have focused primarily on the assembler. In chapter 2, assembler directives were discussed along with their relationship to the positioning of code in an executable. The various sections of where code and data reside have well defined semantics in the Executable and Linkable Format specification. In this chapter, these semantics and the linking process will be examined in more detail.


RISC-V Bare Metal Programming Chapter 2: OpCodes Assemble!

Submitted by MarcAdmin on Wed, 11/06/2019 - 08:03
The previous chapter of this tutorial went over the steps required to setup a RISC-V development environment to create a program that runs on a bare metal VirtIO board using QEMU. Even though the example program – which calculates the sum two integers – was written in RISC-V assembly, no prior knowledge was required to follow along. This chapter will dive into the details of RISC-V assembly language as well as expand on what exactly is happening at each step of the development. The topics covered in this chapter will include an overview of the RISC-V architecture, its assembly instructions, pseudo-instructions, and directives.


RISC-V Bare Metal Programming Chapter 1: The Setup

Submitted by MarcAdmin on Fri, 11/01/2019 - 21:27
In this tutorial, we will walk through the process of building and running a RISC-V program on bare metal hardware; or more specifically emulated hardware. I assume that the reader is familiar with the GNU toolchain and basic C programming. Assembly experience is useful but should not be required to follow along.